Hardware Reference
In-Depth Information
56
else if (remt) nx_state <= chirp3;
57
else nx_state <= armed;
58
end
59
alarm: begin
60
siren <= 1'b1;
61
tmax <= 0;
62
if (remt) nx_state <= chirp2;
63
else nx_state <= alarm;
64
end
65
chirp2: begin
66
siren <= 1'b0;
67
tmax <= chirpOFF-1;
68
if (t==tmax) nx_state <= chirp3;
69
else nx_state <= chirp2;
70
end
71
chirp3: begin
72
siren <= 1'b1;
73
tmax <= chirpON-1;
74
if (t==tmax) nx_state <= chirp4;
75
else nx_state <= chirp3;
76
end
77
chirp4: begin
78
siren <= 1'b0;
79
tmax <= chirpOFF-1;
80
if (t==tmax) nx_state <= chirp5;
81
else nx_state <= chirp4;
82
end
83
chirp5: begin
84
siren <= 1'b1;
85
tmax <= chirpON-1;
86
if (t==tmax) nx_state <= wait2;
87
else nx_state <= chirp5;
88
end
89
wait2: begin
90
siren <= 1'b0;
91
tmax <= 0;
92
if (~remt) nx_state <= disarmed;
93
else nx_state <= wait2;
94
end
95
endcase
96
97 endmodule
98 //-------------------------------------------------------------
10.6 Design of a Triggered Monostable Circuit
This section presents a SystemVerilog-based design for the triggered monostable circuit
of i gure 8.24b, which is capable of generating the signal of i gure 8.24a. Again, the
code that follows is a straightforward application of the SystemVerilog template for
category 2 Moore machines introduced in section 10.2. Note, however, that in this
FSM the timer control strategy #2 (section 8.5.3) cannot be used. Indeed, even strategy
#1 (section 8.5.2) cannot be applied completely because in one of the state transitions
the timer must not be zeroed.
