Hardware Reference
In-Depth Information
In this kind of application, the “−1” term present in the dei nition of the total time
(lines 16, 39, 44, 49, . . .) does not make any difference, but it was maintained as a
reminder of the precise value. Also, in this application possible glitches during (posi-
tive) clock transitions are not a problem, so the optional output register shown in the
last part of the template was not employed.
The reader is invited to compile this code and play with the circuit in the FPGA
development board. Also, check whether the number of DFFs inferred by the compiler
matches the prediction made in section 8.11.2 for each encoding style.
1 //Module header:-----------------------------------
2 module light_rotator (
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input logic stp, clk, rst,
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output logic [6:0] ssd);
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6 //Declarations:-------------------------------------
7
8
//FSM-related declarations:
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typedef enum logic [3:0] {A, AB, B, BC, C, CD, D, DE, E, EF,
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F, FA} state;
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state pr_state, nx_state;
12
13
//Timer-related declarations:
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const logic [22:0] T1 = 6_000_000; //120ms @fclk=50MHz
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const logic [22:0] T2 = 1_750_000; //35ms @fclk=50MHz
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const logic [22:0] tmax = T1-1; //tmax≥max(T1,T2)-1
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logic [22:0] t;
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19 //Statements:-----------------------------------------
20
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//Timer (using strategy #1):
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always_ff @(posedge clk, posedge rst)
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if (rst) t <= 0;
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else if (~stp) begin
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if (pr_state != nx_state) t <= 0;
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else if (t != tmax) t <= t + 1;
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end
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//FSM state register:
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always_ff @(posedge clk, posedge rst)
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if (rst) pr_state <= A;
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else pr_state <= nx_state;
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//FSM combinational logic:
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always_comb
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case (pr_state)
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A: begin
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ssd <= 7'b0111111;
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if (t>=T1-1) nx_state <= AB; //or t==T1-1
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else nx_state <= A;
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end
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AB: begin
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ssd <= 7'b0011111;
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if (t>=T2-1) nx_state <= B; //or t==T2-1
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else nx_state <= AB;
