Hardware Reference
In-Depth Information
10 SystemVerilog Design of Timed (Category 2) State Machines
10.1 Introduction
This chapter presents several SystemVerilog designs of category 2 state machines. It
starts by presenting two SystemVerilog templates, for Moore- and Mealy-based imple-
mentations, which are used subsequently to develop a series of designs related to the
examples introduced in chapter 8.
The codes are all complete (not only partial sketches) and are accompanied by
comments and simulation results, illustrating the design's main features. All circuits
were synthesized using Quartus II (from Altera) or ISE (from Xilinx). The simulations
were performed with Quartus II or ModelSim (from Mentor Graphics). The default
encoding scheme for the states of the FSMs was regular sequential encoding (see
encoding options in section 3.7).
The same designs were developed in chapter 9 using VHDL, so the reader can make
a direct comparison between the codes.
Note : See suggestions of SystemVerilog topics in the bibliography.
10.2 SystemVerilog Template for Timed (Category 2) Moore Machines
The template is presented below. Because it is an extension to the Moore template for
category 1, described in section 7.3, a review of that template is suggested before this
one is examined because only the differences are described.
The only differences are those needed for the inclusion of a timer (external to the
FSM—see i gure 8.2a). Recall, however, that the FSM itself is responsible for controlling
the timer. For that purpose, two strategies were developed in chapter 8, being the i rst
generic (section 8.5.2), and the second (section 8.5.3), non-generic. It is very important
that the reader review those two sections before proceeding.
The i rst of the two templates that follow is for timed Moore machines with the
timer implemented using strategy #1. The timer-related constants ( T 1 , T 2 , . . .) can be
Search WWH ::




Custom Search