Hardware Reference
In-Depth Information
d) Design the circuit using VHDL. Enter the multisignal debouncer as a
component
in
the main code. After compilation, check whether the inferred number of DFFs matches
your prediction.
e) Physically test your design in the FPGA development board. Test it for the following
passwords:
abc
,
aad
, and
aaa
(where
a
= “0111”,
b
= “1011”,
c
= “1101”, and
d
=
“1110”).
Exercise 9.10: Triggered Circuits
This exercise concerns the triggered FSMs treated in exercise 8.17.
a) Solve exercise 8.17 if not done yet.
b) Using VHDL, implement the FSM devised in part a of that exercise. Check whether
the number of DFFs inferred by the compiler matches your prediction. Show corre-
sponding simulation results.
c) Do the same for the FSM of part b in that exercise.
Exercise 9.11: Pulse Shifter
This exercise concerns the pulse shifter of i gure 8.26a. Implement it using VHDL.
Simulate it using the same stimuli of i gure 8.26b and check whether the same wave-
forms result.
Exercise 9.12: Synchronous Pulse Stretcher
This exercise concerns the synchronous pulse stretcher introduced in i gure 8.28a.
a) How many DFFs are needed to build it for
T
= 64 clock cycles and sequential
encoding?
b) Implement it using VHDL. Check whether the number of DFFs inferred by the
compiler matches your estimate.
c) Recompile it for
T
= 5 and simulate it with the same stimuli of i gure 8.28b, check-
ing if the same waveforms result.
Exercise 9.13: Asynchronous Pulse Stretcher
This exercise concerns the asynchronous pulse stretcher introduced in i gure 8.28c.
a) How many DFFs are needed to build it for
T
= 64 clock cycles and sequential
encoding?
b) Implement it using VHDL. Check whether the number of DFFs inferred by the
compiler matches your estimate.
c) Recompile it for
T
= 5 and simulate it with the same stimuli of i gure 8.28d, check-
ing if the same waveforms result.
