Hardware Reference
In-Depth Information
clock for the present circuit. Note that a debouncer is indispensable for the speed
pushbutton.
a) Draw a block diagram for your circuit, including the pushbutton, clock divider, and
FSMs.
b) Draw the state transition diagram for each FSM to be used in the design.
c) Estimate the number of DFFs that will be needed to build the entire circuit.
d) Implement the circuit using VHDL. Check whether the number of DFFs inferred by
the compiler matches your prediction.
e) Physically demonstrate your design in the FPGA development board.
Suggestion: Before solving this problem, solve exercises 9.3 and 9.4 if not done yet.
Exercise 9.6: Light Rotator with Additional Features
This exercise concerns the light rotator of i gure 8.14, to which the following features
must be added:
i
) An input called
dir
(produced by a switch) that selects the rotating direction (clock-
wise when
dir
= '1', counterclockwise otherwise).
ii
) An input called
spd
(produced by a pushbutton) that selects the rotating speed, as
in exercises 9.4 and 9.5. Every time the pushbutton is pressed, the next speed must
be selected. The speed is determined by the time interval during which the machine
stays in states A, B, C, . . . , which must be one of the following: 250, 180, 130, 100,
70, or 40 ms. The duration of states AB, BC, CD, . . . must be always 20 ms. Note
that a debouncer is necessary for the speed pushbutton.
As in exercises 9.4 and 9.5, the system clock should be divided down, producing a
1-kHz clock for the present circuit. (Suggestion: Before solving this problem, solve
exercises 9.4 and 9.5 if not done yet.)
a) Draw a block diagram for your circuit.
b) Draw the state transition diagram for each FSM to be used in the design.
c) Estimate the number of DFFs that will be needed to build the entire circuit. Assume
sequential encoding for the FSM(s).
d) Design the circuit using VHDL. Check whether the number of DFFs inferred by the
compiler matches your prediction.
e) Physically demonstrate your design in the FPGA development board.
Exercise 9.7: Garage Door Controller
This exercise concerns the garage door controller seen in section 5.4.5, designed with
VHDL and SystemVerilog in sections 6.7 and 7.6, respectively. Make the modii cations
