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d) Physically test your design in the FPGA development board for several switches
(both toggle and pushbutton types).
Exercise 9.4: Reference-Value Defi ner
This exercise concerns the reference-value dei ner of i gure 8.17b, which must produce
the following consecutive values (the value must change every time the pushbutton
is pressed): 250, 180, 130, 100, 70, and 40 (thus ref is an eight-bit signal). These values
must be displayed on your development board using either three SSDs or eight LEDs
(if the former is chosen, an SSD driver must be included in the design). In this exercise
it is requested that the clock frequency be divided down to 1 kHz; this 1-kHz signal
( clk1k ) is the clock to be employed in the circuit.
a) Assume a 3-ms debouncing interval. Consequently, only four consecutive equal
readings are needed for the pushbutton value to be considered valid. Is an FSM still
desired for the debouncer (plus one-shot conversion)? If so, does it need to be a timed
machine, as in i gure 8.18b?
b) Draw a block diagram for your circuit, including in it the clock divider and the
output display.
c) Draw the state transition diagram for each FSM used in the design.
d) Estimate the number of DFFs that will be needed to build the entire circuit (includ-
ing the clock divider). Assume sequential encoding for the FSM(s) and check the clock
frequency in your development board.
e) Implement the circuit using VHDL. Check whether the number of DFFs inferred by
the compiler matches your prediction.
f) Physically demonstrate your design in the FPGA development board.
Exercise 9.5: Blinking Light with Several Speeds
This exercise is an extension to the light blinker of i gure 8.12c, which must
now operate with a programmable speed, set by a pushbutton, called spd (see the
general diagram of i gure 9.4). The next speed must be selected every time the
pushbutton is pressed. The speed is determined by the on-off time interval ( T ref ),
which must be one of the following: 250, 180, 130, 100, 70, or 40 ms. As in exercise
9.4, the frequency of the system clock should be divided down, producing a 1-kHz
Figure 9.4
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