Hardware Reference
In-Depth Information
61
when B =>
62
y <= '0';
63
if x='1' then
64
nx_state <= C;
65
else
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nx_state <= B;
67
end if;
68
when C =>
69
y <= '1';
70
if x='0' and t<delay-1 then
71
nx_state <= D;
72
elsif x='0' and t>=delay-1 then
73
nx_state <= B;
74
elsif x='1' and t>=delay-1 then
75
nx_state <= A;
76
else
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nx_state <= C;
78
end if;
79
when D =>
80
y <= '1';
81
if x='1' then
82
nx_state <= C;
83
elsif x='0' and t>=delay-2 then
84
nx_state <= B;
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else
86
nx_state <= D;
87
end if;
88
end case;
89
end process;
90
91
--Optional output register:
92
process (clk)
93
begin
94
if rising_edge(clk) then
95
y_reg <= y;
96
end if;
97
end process;
98
99 end architecture;
100 -------------------------------------------------------
9.7 Exercises
Exercise 9.1: Timer Control Strategies Analysis (Light Rotator)
This exercise concerns the light rotator of i gure 8.14b, implemented with VHDL in
section 9.4.
a) Compile the code of section 9.4 for the following options and write down the
number of logic elements and registers inferred by the compiler in each case: 1) Using
strategy #1 for the timer and sequential encoding for the machine; 2) With strategy
#1 and one-hot encoding; 3) With strategy #2 and sequential encoding; 4) With strat-
egy #2 and one-hot encoding.
