Hardware Reference
In-Depth Information
5 entity triggered_mono is
6 port (
7 x, clk, rst: in std_logic;
8 y: buffer std_logic;
9 y_reg: out std_logic);
10 end entity;
11 -------------------------------------------------------
12 architecture moore_fsm of triggered_mono is
13
14
--FSM-related declarations:
15
type state is (A, B, C, D);
16
signal pr_state, nx_state: state;
17
18
--Timer-related declarations:
19
constant delay: natural := 3; --any value >=2
20
signal t: natural range 0 to delay-1; --tmax≥delay-1
21
22 begin
23
24
--Timer (strategy #1, adapted):
25
process (clk, rst)
26
begin
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if rst='1' then
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t <= 0;
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elsif rising_edge(clk) then
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if pr_state /= nx_state then
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if nx_state/=D then
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t <= 0;
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end if;
34
elsif t/=delay-1 then
35
t <= t + 1;
36
end if;
37
end if;
38
end process;
39
40
--FSM state register:
41
process (clk, rst)
42
begin
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if rst='1' then
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pr_state <= A;
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elsif rising_edge(clk) then
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pr_state <= nx_state;
47
end if;
48
end process;
49
50
--FSM combinational logic:
51
process (all)
52
begin
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case pr_state is
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when A =>
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y <= '0';
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if x='0' then
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nx_state <= B;
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else
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nx_state <= A;
60
end if;
