Hardware Reference
In-Depth Information
from a DFF (hence glitch-free), that is not guaranteed because it depends on the encod-
ing scheme used in the machine.
Observe the correct use of registers and the completeness of the code, as described
in comment 10 of section 6.3. Note in particular the following:
1) Regarding the use of registers: The circuit is not overregistered. This can be observed
in the
elsif rising_edge(clk)
statement of line 45 (responsible for the inference of
l ip-l ops), which is closed in line 47, guaranteeing that only the machine state (line
46) gets stored (besides the timer and the output register, of course, designed in other
processes). The output (
y
) is in the next process, which is purely combinational (thus
not registered).
2) Regarding the outputs: The list of outputs (just
y
in this example) is exactly the
same in all states (see lines 55, 62, 69, . . .), and the corresponding values are always
properly declared.
3) Regarding the next state: Again, the coverage is complete because all states are
included (see lines 54, 61, 68, . . .), and in each state the conditional declarations for
the next state are always i nalized with an
else
statement (lines 58, 65, 76, . . .), guar-
anteeing that no condition is left unchecked.
The total number of l ip-l ops inferred by the compiler on synthesizing the code
below, with regular sequential encoding for the machine states, was 5 for
T
= 3 and
15 for
T
= 3000.
Simulation results, for
T
= 3 clock cycles, are depicted in i gure 9.2. Analyze the
plots to coni rm the correctness of the circuit operation.
1 ----------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 ----------------------------------------------------
Figure 9.2
Simulation results from the VHDL code for the triggered monostable circuit of i gure 8.24b for
T
= 3 clock periods.
