Hardware Reference
In-Depth Information
129 tmax <= 0;
130 if remt='0' then
131 nx_state <= disarmed;
132 else
133 nx_state <= wait2;
134 end if;
135 end case;
136 end process;
137
138 end architecture;
139 ------------------------------------------------------------------
9.6 Design of a Triggered Monostable Circuit
This section presents a VHDL-based design for the triggered monostable circuit of
i gure 8.24b, which is capable of generating the signal of i gure 8.24a. Again, the code
that follows is a straightforward application of the VHDL template for category 2
Moore machines introduced in section 9.2. Note, however, that in this FSM the timer
control strategy #2 (section 8.5.3) cannot be used. Indeed, even strategy #1 (section
8.5.2) cannot be applied completely because in one of the state transitions the timer
must not be zeroed.
The entity, called
triggered_mono
, is in lines 5-10. All ports are of type
std_logic
(industry standard).
The architecture, called
moore_fsm
, is in lines 12-99. As usual, it contains a declara-
tive part and a statements part, with four processes in the latter.
The declarative part of the architecture (lines 14-20) contains FSM- and timer-
related declarations. In the former the enumerated type
state
is created to represent
the machine's present and next states. In the latter a small value was used for
T
(called
delay
in the code; note
delay
= 3 in line 19) in order to ease the inspection of the simu-
lation results (shown later).
The i rst process (lines 25-38) implements the timer (with strategy #1, adapted).
Observe how the timer is prevented from being zeroed when the machine enters state
D, done with just the introduction of lines 31 and 33.
The second process (lines 41-48) implements the state register, exactly as in the
template.
The third process (lines 51-89) implements the entire combinational logic section.
It is just a list of all states, each containing the output (
y
) value and the next state.
Note that in each state the output value is unique because in a Moore machine the
output depends only on the state in which the machine is.
The fourth and i nal process (lines 92-97) implements the optional output register,
exactly as in the template. The output register was included because in this kind of
application glitches are generally not acceptable. Even though
y
could come directly
