Hardware Reference
In-Depth Information
92
...
93
when F =>
94
...
95
when FA =>
96
ssd <= "0111101";
97
if t=T2-1 then
98
nx_state <= A;
99
else
100
nx_state <= FA;
101
end if;
102
end case;
103
end process;
104
105 end architecture;
106 -----------------------------------------------------------
9.5 Design of a Car Alarm (with Chirps)
This section presents a VHDL-based design for the car alarm with chirps introduced
in section 8.11.6. The Moore template of section 9.2 is employed to implement the
FSM of i gure 8.21c. Again, either strategy #1 or #2 can be used to build the timer; the
latter was adopted in the code below.
The entity, called car_alarm_with_chirps , is in lines 5-9. All ports are of type std_logic
(industry standard).
The architecture, called moore_fsm , is in lines 11-138. As usual, it contains a declara-
tive part and a statements part, with three processes in the latter.
The declarative part of the architecture (lines 13-21) contains FSM- and timer-
related declarations. In the former the enumerated type state is created to represent
the machine's present and next states. In the latter the value chosen for chirpON and
chirpOFF is such that the chirp and the time interval between chirps last 0.3 s, assum-
ing f clk = 50 MHz.
The i rst process (lines 26-37) implements the timer, using strategy #2, exactly as
in the template.
The second process (lines 40-47) implements the state register, again exactly as in
the template.
The third and i nal process (lines 50-136) implements the entire combinational
logic section. It is just a list of all states, each containing the output ( siren ) value, the
value of t max , and the next state. Note that in each state the output value is unique
because in a Moore machine the output depends only on the state in which the
machine is.
In this kind of application the “
1” term present in the determination of t max (lines
21, 63, 97, . . .) does not make any difference, but it was maintained as a reminder of
the accurate value.
Observe the correct use of registers and the completeness of the code, as described
in comment 10 of section 6.3. Note in particular the following:
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