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35
end if;
36
end if;
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end process;
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--FSM state register:
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process (clk, rst)
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begin
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if rst='1' then
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pr_state <= A;
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elsif rising_edge(clk) then
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pr_state <= nx_state;
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end if;
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end process;
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--FSM combinational logic:
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process (all)
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begin
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case pr_state is
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when A =>
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ssd <= "0111111";
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if t>=T1-1 then -- or t=T1-1
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nx_state <= AB;
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else
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nx_state <= A;
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end if;
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when AB =>
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ssd <= "0011111";
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if t>=T2-1 then -- or t=T2-1
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nx_state <= B;
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else
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nx_state <= AB;
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end if;
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when B =>
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ssd <= "1011111";
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if t>=T1-1 then
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nx_state <= BC;
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else
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nx_state <= B;
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end if;
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when BC =>
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ssd <= "1001111";
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if t>=T2-1 then
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nx_state <= C;
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else
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nx_state <= BC;
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end if;
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when C =>
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...
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when CD =>
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...
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when D =>
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...
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when DE =>
88
...
89
when E =>
90
...
91
when EF =>
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