Hardware Reference
In-Depth Information
50
elsif ... then
51
nx_state <= ...;
52
else
53
nx_state <= A;
54
end if;
55
when B =>
56
output1 <= <value>;
57
output2 <= <value>;
58
...
59
tmax <= T2-1;
60
if ... and t=tmax then
61
nx_state <= C;
62
elsif ... then
63
nx_state <= ...;
64
else
65
nx_state <= B;
66
end if;
67
when C =>
68
...
69
end case;
70
end process;
71
72
--Optional output register:
73
(same as for category 1 Moore, section 6.3)
74
75 end architecture;
76 -----------------------------------------------------------------
9.3 VHDL Template for Timed (Category 2) Mealy Machines
The template is presented below, using strategy #1 to implement the timer. The only
difference with respect to the Moore template (section 9.2) is in the process for the
combinational logic block (lines 20-60) because the outputs are specii ed differently
here (see the template for category 1 Mealy machines in section 6.5). Recall that in a
Mealy machine the output depends not only on the FSM's state, but also on the input,
so if statements are expected for the output in one or more states because the output
values might not be unique.
Please review the following comments, which can be easily adapted from the Moore
case to the Mealy case:
—On the Moore template for category 1, in section 6.3, especially comment 10.
—On the enum_encoding and fsm_encoding attributes, also in section 6.3.
—On possible code variations, in section 6.4.
—On the Mealy template for category 1, in section 6.5.
—On the Moore templates for category 2, in section 9.2.
1 --Timed Mealy machine with timer control strategy #1----
2 library ieee;
3 use ieee.std_logic_1164.all;
4 ---------------------------------------------------------
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