Hardware Reference
In-Depth Information
9 VHDL Design of Timed (Category 2) State Machines
9.1 Introduction
This chapter presents several VHDL designs of category 2 state machines. It starts by
presenting two VHDL templates, for Moore- and Mealy-based implementations, which
are used subsequently to develop a series of designs related to the examples introduced
in chapter 8.
The codes are always complete (not only partial sketches) and are accompanied by
comments and simulation results, illustrating the design's main features. All circuits
were synthesized using Quartus II (from Altera) or ISE (from Xilinx). The simulations
were performed with Quartus II or ModelSim (from Mentor Graphics). The default
encoding scheme for the states of the FSMs was regular sequential encoding (see
encoding options in section 3.7; see ways of selecting the encoding scheme at the end
of section 6.3).
The same designs are presented in chapter 10 using SystemVerilog, so the reader
can make a direct comparison between the codes.
Note:
See suggestions of VHDL topics in the bibliography.
9.2 VHDL Template for Timed (Category 2) Moore Machines
The template is presented below. Because it is an extension to the Moore template for
category 1, described in section 6.3, a review of that template is suggested before this
one is examined because only the differences are described.
The only differences are those needed for the inclusion of a timer (external to the
FSM—see i gure 8.2a). Recall, however, that the FSM itself is responsible for controlling
the timer. For that purpose, two strategies were developed in chapter 8, being the i rst
generic (section 8.5.2), and the second (section 8.5.3), non-generic. It is very important
that the reader review those two sections before proceeding.
