Hardware Reference
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a) Explain why both strategies #1 and #2 (section 8.5) are appropriate to implement
the timer in this machine. What are the advantages and disadvantages of each one?
b) Is a reset signal needed? Explain. (Suggestion: Review sections 3.8 and 3.9.)
c) Is key an asynchronous input? (Suggestion: Review section 2.3.)
d) If key has already been processed by a debouncer (as in exercise 8.11), are synchro-
nizers needed?
e) Why is the state ready needed in this FSM?
f) Why must the machine not go back to the idle state as soon as a wrong key is
punched in?
Exercise 8.16: Triggered Circuits #1
The questions below concern the pulse generator of i gure 8.24b, which produces the
signal of i gure 8.24a.
a) How many l ip-l ops are needed to build that circuit, for T = 3 clock cycles, sequen-
tial encoding, and not including the optional output register?
b) In which states is the timer not needed? How should the timer be operated in those
states?
c) Complete the plots of i gure 8.36 (for T = 3) and then comment on the results.
Exercise 8.17: Triggered Circuits #2
Two signals produced by triggered circuits are exhibited in i gure 8.37.
Figure 8.36
Figure 8.37
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