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synchronous (Moore) machine operating at the negative clock transition. The former
option can be implemented with the FSM of i gure 8.28c, with T = N . Note also that
done can be computed as ena
. Another serial data receiver will be seen in section 11.7.7.
8.12 Exercises
Exercise 8.1: Machines Category
a) Why are the state machines in i gures 8.12c, 8.14b, 8.20c, and 8.21c (among others)
said to be of category 2?
b) What differentiates category 2 from category 1? (Compare i gures 8.2 and 5.2.)
Exercise 8.2: Timer Interpretation #1
Consider the timed machine of i gure 8.3, operating with f clk = 1 MHz and T = 13 clock
cycles.
a) Which states are timed (timer needed) and which are not?
b) Can any of the states last longer than T clock periods? Explain.
c) Can the timer control strategy #2 (section 8.5.3) be used to build the timer?
d) Since T = 13, we know that the range of interest is from 0 to 12. Assuming that
strategy #1 (section 8.5.2) is adopted to build the timer, can we employ a timer that
runs (when enabled, of course) up to 16 (a power of two)? What are the consequences
of this?
e) Still assuming strategy #1 for the timer, is it necessary to specify a value for T (= 0,
for example) in the untimed states? Is that the case also in strategy #2?
f) During how many microseconds will the machine stay in each state? Does your
answer depend on x ?
g) How many l ip-l ops are needed to build this FSM (with sequential encoding),
including the timer? Does this answer depend on x ?
Exercise 8.3: Timer Interpretation #2
Consider the timed machine of i gure 8.3, operating with T = 3 clock cycles. Fill in
the missing parts in the plots of i gure 8.30. Note the intentional propagation delays
left between the clock transitions and the respective responses to portray a realistic
Figure 8.30
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