Hardware Reference
In-Depth Information
8.10 Number of Flip-Flops
Having understood the timer, we pass now to the last analysis before the presentation
of timed (category 2) FSM examples. The analysis regards the number of l ip-l ops
needed to implement the intended circuit. As mentioned earlier, in general, and par-
ticularly in large designs, it is difi cult to estimate the number of logic gates that will
be needed to implement the desired solution, but it is always possible to determine,
and exactly, the number of l ip-l ops.
In the particular case of sequential circuits implemented as category 2 state
machines, there are three demands for DFFs, as follows.
1) For the state register (see
nx_state
and
pr_state
in i gure 8.2a, which are the
state memory l ip-l ops' input and output, respectively; below,
M
FSM
is the number of
states):
For sequential or Gray encoding,
N
FSM
=
໌
log
2
M
FSM
ໍ
. For example,
M
FSM
= 25
→
N
FSM
= 5.
For Johnson encoding,
N
FSM
=
໌
M
FSM
/2
ໍ
. For example,
M
FSM
= 25
→
N
FSM
= 13.
N
FSM
= 25.
2) For the output register (i gure 8.2b, optional, with
b
output
bits):
N
output
=
b
output
. For example,
b
output
= 16
For one-hot encoding,
N
FSM
=
M
FSM
. For example,
M
FSM
= 25
→
N
output
= 16.
3) To build the timer (i gure 8.2a, compulsory):
N
timer
=
໌
log
2
T
max
ໍ
, where
T
max
is the largest transition time, expressed in “number
of clock cycles,” that is,
T
max
=
t
state_max
→
f
clk
, where
t
state_max
is the largest transition
time, in seconds, and
f
clk
is the clock frequency, in hertz. For example, for the
machine to be able to stay
t
state_max
= 8
×
s in the state with longest duration, and
assuming that
f
clk
= 50 MHz,
T
max
= 8·10
-6
μ
×
50·10
6
= 400 clock cycles must be used,
from which
N
timer
= 9 results.
Therefore, the total number of DFFs is
N
total
=
N
FSM
+
N
output
+
N
timer
. In the examples
that follow, as well as in the actual designs with VHDL and SystemVerilog, the number
of l ip-l ops will be often examined.
8.11 Examples of Timed (Category 2) Machines
A series of timed FSMs are presented next. To draw the corresponding state transition
diagrams, strategy #1 (section 8.5.2) is considered as the default strategy for controlling
the timer. If the resulting machine fuli lls condition 1 or 2 for strategy #2 (section
8.5.3), then that strategy too can be used to control the timer.
Several of the examples described in this chapter will be implemented later using
VHDL (chapter 9) and SystemVerilog (chapter 10).
