Hardware Reference
In-Depth Information
8.3 Timer Interpretation
It is very important to interpret the timer correctly. The analysis below and that in
the section that follows are based on the state machine of i gure 8.3, where
x
is the
actual input,
t
is an auxiliary input generated by a timer (see the timer in i gure 8.2a),
and
y
is the actual output. Note that this FSM contains all four possible transition
types (see section 1.6).
8.3.1 Time Measurement Unit
The time in timed machines (
t
and
T
in i gure 8.3, for example) is not expressed in
seconds but rather in “number of clock cycles.” For example, if we want the machine
to stay in a certain state during
t
state
= 2 ms, and the clock frequency is
f
clk
= 50 MHz,
we simply adopt
T
=
t
state
×
f
clk
= 2·10
-3
×
50·10
6
= 100,000 clock cycles.
8.3.2 Timer Range
If a regular sequential counter with initial value zero is used to build the timer, the
counter's range for the timer to span
T
clock periods is then from
t
= 0 to
t
=
T
−
1
1).
If the machine has multiple timed transitions, requiring it to stay
T
1
clock cycles
in state S
1
,
T
2
clock cycles in state S
2
, and so on, then the value of
T
can be determined
using the expression
T
= max {
T
1
,
T
2
, . . .}. The same is true if multiple values of
T
are
required in the same state.
Note that indeed a counter running up to any value above
t
max
would also do. For
example, one could choose to use a timer that runs up to the next power-of-two, in
which case only the counter's MSB would need to be monitored, simplifying the circuit
construction (at the expense of an extra DFF; also, the transition conditions should
be changed from
t
=
t
max
to
t
(so
t
max
=
T
−
≥
t
max
in the conditional-timed cases).
8.3.3 Number of Bits
The number of bits needed to implement the timer is
N
=
໌
log
2
T
ໍ
. In other words,
N
must satisfy
T
≤
2
N
. For example, if we want
T
1
= 25 and
T
2
= 8,
T
= max {25, 8} = 25
Figure 8.3
State machine with all four possible transition types.
