Hardware Reference
In-Depth Information
Figure 8.2
Timed (category 2) state machine architectures. (a) Moore or Mealy type (depending on input
connections). (b) Optional output register. (c) Resulting circuits.
an extra input. Because the output depends only on the state in which the machine
is, this circuit is synchronous (see details in section 3.5). Because modern designs are
generally synchronous, this option is preferred over any other timed implementation
whenever the application permits.
Timed Mealy machine
: Again, the circuit of i gure 8.2a is used, but this time with the
input connected to both logic blocks (for output and for next state), as in i gure 5.2b.
Consequently, it behaves exactly as a pure Mealy machine, just with an auxiliary timer
operating as an extra input. Because the input-output transfer is asynchronous, this
machine can have more than one output value for the same state (see details in section
3.5).
Out-registered (pipelined) timed Moore machine
: The extra register of i gure 8.2b is con-
nected to the output of the timed Moore machine. As seen in sections 2.5 and 2.6,
two fundamental reasons for doing so are glitch removal and pipelined construction.
The new output will be one or one-half of a clock cycle (depending on the selected
clock edge) behind the original output. The resulting circuit is order-2 synchronous
because the original Moore machine was already a registered circuit (in other words,
the input-output transfer occurs after two clock edges—see details in section 3.5). If
in a given application this extra register is needed but its consequent extra delay is
not acceptable, the next alternative can be considered.
Out-registered (pipelined) timed Mealy machine
: The extra register of i gure 8.2b is
connected to the output of the timed Mealy machine. The reasons for doing so
are the same as for Moore machines. The resulting circuit is order-1 synchronous
because the input-output relationship in the original Mealy machine can be asyn-
chronous. Consequently, the overall behavior (with the output register included) is
similar to that of a timed Moore machine without the output register (see details in
section 3.5).
