Hardware Reference
In-Depth Information
Figure 8.1
State machine categories (from a hardware perspective).
2) The state machine type (Moore or Mealy).
It is important to recall, however, that regardless of the machine category and type,
the state transition diagram must fuli ll three fundamental requisites (seen in section
1.3):
1) It must include all possible system states.
2) All state transition conditions must be specii ed (unless a transition is uncondi-
tional) and must be truly complementary.
3) The list of outputs must be exactly the same in all states (standard architecture).
8.2 Architectures for Timed (Category 2) Machines
The general architecture for category 2 machines is summarized in i gure 8.2a. This
representation follows the style of i gures 3.1b and 3.1d, but the style of i gures 3.1a
and 3.1c could be used equivalently. The output register (i gure 8.2b) is still optional,
but the timer (in i gure 8.2a) is compulsory.
Note that the timer operates as an auxiliary circuit, producing the signal
t
, needed by
the state machine. However, the FSM itself is responsible for controlling the timer, as
represented symbolically by the control signal
ctr
in the i gure. In other words, the
machine is who decides when the timer should run or stop and when it should be zeroed.
The four possible constructions, listed in i gure 8.2c, are summarized below.
Timed Moore machine
: The circuit of i gure 8.2a is used with the input (if it exists) con-
nected only to the logic block for the next state, as in i gure 5.2a. Consequently, it
behaves exactly as a pure Moore machine, just with an auxiliary timer operating as
