Hardware Reference
In-Depth Information
4
output logic [2:0] outp);
5
6 //Declarations:-------------------------------------------------
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//FSM states type:
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typedef enum logic [2:0] {one, two, three, four, five} state;
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state pr_state, nx_state;
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11 //Statements:---------------------------------------------------
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//FSM state register:
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always_ff @(posedge clk, posedge rst)
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if (rst) pr_state <= one;
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else pr_state <= nx_state;
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//FSM combinational logic:
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always_comb
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case (pr_state)
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one: begin
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outp <= 1;
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if (ena)
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if (up) nx_state <= two;
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else nx_state <= five;
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else nx_state <= one;
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end
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two: begin
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outp <= 2;
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if (ena)
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if (up) nx_state <= three;
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else nx_state <= one;
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else nx_state <= two;
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end
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three: begin
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outp <= 3;
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if (ena)
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if (up) nx_state <= four;
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else nx_state <= two;
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else nx_state <= three;
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end
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four: begin
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outp <= 4;
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if (ena)
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if (up) nx_state <= five;
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else nx_state <= three;
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else nx_state <= four;
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end
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five: begin
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outp <= 5;
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if (ena)
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if (up) nx_state <= one;
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else nx_state <= four;
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else nx_state <= five;
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end
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endcase
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57 endmodule
58 //--------------------------------------------------------------
