Hardware Reference
In-Depth Information
53
C: ...
54
...
55
endcase
56
57
//Optional output register:
58
(same as for category 1 Moore, section 7.3)
59
60 endmodule
61 //--------------------------------------------------------
7.5 Design of a Small Counter
This section presents a SystemVerilog-based design for the 1-to-5 counter with enable
and up-down controls introduced in section 5.4.1 (i gure 5.3).
Because counters are inherently synchronous, the Moore approach is the natural
choice for their implementation, so the SystemVerilog template of section 7.3 is used.
Because possible glitches at (positive) clock transitions are generally not a problem in
counters, the optional output register shown in the i nal portion of the template is
not employed.
The i rst part of the code (
module header
) is in lines 1-4. The module's name is
counter
. Note that all ports are of type
logic
, with one bit for each input and three bits
for the output.
The second part of the code (
declarations
) is in lines 6-9. The enumerated type
state
is created in it to represent the machine's present and next states.
The third and i nal part of the code (
statements
) is in lines 11-57. It contains two
always
blocks, described next.
The i rst
always
block (lines 13-15) is an
always_ff
, which implements the
machine's state register. This is a standard code, similar to the template.
The second
always
block (lines 18-55) is an
always_comb
, which implements the
entire combinational logic section. It is just a list of all states, each containing the
output value and the next state. Note that in each state the output value is unique
because in a Moore machine the output depends only on the state in which the
machine is.
Finally, and very importantly, observe the correct use of registers and the complete-
ness of the code, as described in comment 8 of section 7.3. Observe in particular the
following: 1) all states are included; 2) the list of outputs (only
outp
in this case) is
exactly the same in all states, and the corresponding values are always included; 3)
the specii cations for
nx_state
are always i nalized with an
else
statement, so no condi-
tion is left unchecked.
1 //Module header:-----------------------------------------------
2 module counter (
3
input logic up, ena, clk, rst,
