Hardware Reference
In-Depth Information
1 --Dangerous template (particular case of the general template)
2 library ieee;
3 use ieee.std_logic_1164.all;
4 ---------------------------------------------------------------
5 entity circuit is
6 generic (...);
7 port (
8 clk, rst: in std_logic;
9 input, ...: in std_logic_vector(...);
10 output, ...: out std_logic_vector(...);
11 end entity;
12 ---------------------------------------------------------------
13 architecture moore_fsm of circuit is
14 type state is (A, B, C, ...);
15 signal fsm_state: state;
16 begin
17 process (clk, rst)
18 begin
19 if rst then
20 fsm_state <= A;
21 elsif rising_edge(clk) then
22 case fsm_state is
23 when A =>
24 output <= <value>;
25 if <condition> then
26 fsm_state <= B;
27 elsif <condition> then
28 fsm_state <= ...;
29 else
30 fsm_state <= A;
31 end if;
32 when B =>
33 output <= <value>;
34 if <condition> then
35 ...
36 else
37 fsm_state <= B;
38 end if;
39 when C =>
40 ...
41 end case;
42 end if;
43 end process;
44 ---------------------------------------------------------------
6.5 VHDL Template for Regular (Category 1) Mealy Machines
This template, also based on i gures 6.1 and 6.2, is presented below. The only differ-
ence with respect to the Moore template just presented is in the process for the com-
binational logic because the output is specii ed differently now. Recall that in a Mealy
machine the output depends not only on the FSM's state but also on its input, so
if
statements are expected for the output in one or more states because the output values
might not be unique. This is achieved by including the output
within
the conditional
