Hardware Reference
In-Depth Information
35 --Default values:
36 output1 <= <value>;
37 output2 <= <value>;
38 ...
39 --Code:
40 case pr_state is
41 when A =>;
42 ...
43 when B =>
44 ...
45 end case;
46 end process;
6.4.4 A Dangerous Template
A tempting template is shown next. Note that the entire FSM is in a single process
(lines 17-43). Its essential point is that the
elsif rising_edge(clk)
statement encloses
the whole circuit (it opens in line 21 and only closes in line 42), thus registering it
completely (that is, not only the state is stored in l ip-l ops—this has to be done
anyway—but also all the outputs).
This template has several
apparent
advantages. One is that a shorter code results
(for instance, we can replace
pr_state
and
nx_state
with a single name—
fsm_state
, for
example; also, only one process is needed). Another apparent advantage is that the
code will work (no latches inferred) when the list of outputs is not exactly the same
in all states. Such features, however, might hide serious problems.
One of the problems is precisely the fact that the outputs are always registered, so
the resulting circuit is never the FSM alone but the FSM plus the optional output
register of i gure 5.2c, which many times is unwanted.
Another problem is that, even if the optional output register were needed, we do
not have the freedom to choose in which of the clock edges to operate it because the
same edge is used for the FSM and for the output register in this template, reducing
the design l exibility.
A third problem is the fact that, because the list of outputs does not need to be the
same in all states (because they are registered, latches will not be inferred when an
output value is not specii ed), the designer is prone to overlook the project
specii cations.
Finally, it is important to remember that VHDL (and SystemVerilog) is not a
program but a code, and a shorter code
does not mean
a smaller or better circuit. In
fact, longer, better-organized codes tend to ease the compiler's work, helping to opti-
mize the i nal circuit.
In summary, the template below is a
particular case
of the general template intro-
duced in section 6.3. The general template gets reduced to this one only when all
outputs must be registered and the same clock edge must operate both the state register
and the output register.
