Hardware Reference
In-Depth Information
45 ...
46 end case;
47 end process;
48
49 --FSM combinational logic for next state:
50 process (all)
51 begin
52 case pr_state is
53 when A =>
54 if <condition> then
55 nx_state <= B;
56 elsif <condition> then
57 nx_state <= ...;
58 else
59 nx_state <= A;
60 end if;
61 when B =>
62 if <condition> then
63 nx_state <= C;
64 ...
65 end if;
66 when C =>
67 ...
68 end case;
69 end process;
6.4.2 State Register Plus Output Register in a Single Process
A variation in the other direction (reducing the number of processes from three to
two instead of increasing it to four) consists of joining the process for the state register
with that for the output register. This is not recommended for three reasons. First, in
most projects the optional output register is not needed. Second, having the output
register in a separate process helps remind the designer that the need or not for such
a register is an important case-by-case decision. Third, one might want to have the
output register operating at the other (negative) clock edge, which is better emphasized
by using separate processes.
6.4.3 Using Default Values
When the same signal or variable value appears several times inside the
same
process,
a default value can be entered at the beginning of the process. An example is shown
below for the process of the combinational logic section, with default values for the
outputs included in lines 36-38. In lines 40-45 only the values that disagree with
these must then be typed in. An example in which default values are used is seen in
section 12.4.
32 --FSM combinational logic:
33 process (all)
34 begin
