Hardware Reference
In-Depth Information
in lines 9-12. Note that the type used for all ports (lines 10-12) is indeed
std_logic
or
std_logic_vector
.
4) The architecture, called
moore_fsm
, is in lines 15-75. It too is divided into two parts:
declarative part (optional) and statements part (code proper, so mandatory).
5) The declarative part of the architecture is in lines 16-19. In lines 16-17 a special
enumerated type, called
state
, is created, and then the signals
pr_state
and
nx_state
are
declared using that type. In lines 18-19 an optional attribute called
enum_encoding
is
shown, which dei nes the type of encoding desired for the machine's states (e.g.,
“sequential”, “one-hot”). Another related attribute is
fsm_encoding
. See a description
for both attributes after the template below. The encoding scheme can also be chosen
using the compiler's setup, in which case lines 18-19 can be removed.
6) The statements part (code proper) of the architecture is in lines 20-75 (from
begin
on). In this template it is composed of three
process
blocks, described below.
7) The i rst process (lines 23-30) implements the state register (process 1 of i gure 6.2).
Because all of the machine's DFFs are in this section, clock and reset are only con-
nected to this block (plus to the optional output register, of course, but that is not
part of the FSM proper). Note that the code for this process is essentially standard,
simply copying
nx_state
to
pr_state
at every positive clock transition (thus inferring
the DFFs that store the machine's state).
8) The second process (lines 33-61) implements the entire combinational logic section
of the FSM (process 2 of i gure 6.2). This part must contain all states (A, B, C, . . .),
and for each state two things must be declared: the output values/expressions and the
next state. Observe, for example, in lines 36-46, relative to state A, the output declara-
tions in lines 37-39 and the next-state declarations in lines 40-46. A very important
point to note here is that there is no
if
statement associated with the outputs because
in a Moore machine the outputs depend solely on the state in which the machine is,
so for a given state each output value/expression is unique.
9) The third and i nal process (lines 64-73) implements the optional output register
(process 3 of i gure 6.2). Note that it simply copies each original output to a new
output at every positive clock edge (it could also be at the negative edge), thus infer-
ring the extra register. If this register is used, then the names of the new outputs must
obviously be the names used in the corresponding port declarations (line 12). If the
initial output values do not matter, reset is not required in this register.
10) To conclude, observe the completeness of the code and the correct use of registers
(as requested in sections 4.2.8 and 4.2.9, respectively), summarized below.
a) Regarding the use of registers: The circuit is not overregistered. This can be
observed in the
elsif rising_edge(clk)
statement of line 27 (responsible for the infer-
ence of l ip-l ops), which is closed in line 29, guaranteeing that only the machine
state (line 28) gets registered. The circuit outputs are in the next process, which is
purely combinational.
