Hardware Reference
In-Depth Information
Figure 6.1
Typical VHDL code structure for synthesis.
Entity
The entity is divided into two main parts, called
generic
and
port
.
Generic:
This portion is optional. It is used for the declaration of global parameters,
which can be easily modii ed to fuli ll different system specii cations or, more impor-
tantly, can be overridden during instantiations (using the
component
construct) into
other designs.
Port:
This part of the code is mandatory for synthesis. It is just a list with specii -
cations of all circuit ports (I/Os), including their name, mode (
in
,
out
,
inout
, or
buffer
),
and type (plus range).
Architecture
The architecture too is divided into two parts, called
declarative part
and
statements part
.
Declarative part:
This section precedes the keyword
begin
and is optional. It is used
for all sorts of local declarations, including
type
,
signal
, and
component
. It also allows
the construction of
function
and
procedure
. These declarations and functions/
procedures can also be placed outside the main code, in a
package
.
Statements part:
This portion, which starts at the keyword
begin
, constitutes the
code proper. As shown in i gure 6.1, its main elements (in no particular order) are
the following: basic expressions using operators (for simple combinational circuits);
expressions using concurrent statements (
when
,
select
,
generate
), generally for simple
