Hardware Reference
In-Depth Information
6 VHDL Design of Regular (Category 1) State Machines
6.1 Introduction
This chapter presents several VHDL designs of category 1 state machines. It starts by
presenting two VHDL templates, for Moore- and Mealy-based implementations, which
are used subsequently to develop a series of designs related to the examples introduced
in chapter 5.
The codes are always complete (not only partial sketches) and are accompanied by
comments and simulation results, illustrating the design's main features. All circuits
were synthesized using Quartus II (from Altera) or ISE (from Xilinx). The simulations
were performed with Quartus II or ModelSim (from Mentor Graphics). The default
encoding scheme for the states of the FSMs was regular sequential encoding (see
encoding options in section 3.7; see ways of selecting the encoding scheme at the end
of section 6.3).
The same designs will be presented in chapter 7 using SystemVerilog, so the reader
can make a direct comparison between the codes.
Note:
See suggestions of VHDL topics in the bibliography.
6.2 General Structure of VHDL Code
A typical structure of VHDL code for synthesis, with all elements that are needed in
this and in coming chapters, is depicted in i gure 6.1. It is composed of three funda-
mental sections, briel y described below.
Library/Package Declarations
As the name says, it contains the libraries and corresponding packages needed in the
design. The most common package is
std_logic_1164
, from the IEEE library, which
dei nes the types
std_logic
(for single bit) and
std_logic_vector
(for multiple bits), which
are the industry standard.
