Hardware Reference
In-Depth Information
Figure 5.15
A “transparent” circuit. (a) Circuit ports. (b) Moore and (c) Mealy state transition diagrams.
(d) Typical implementation based on the Moore model.
overall circuit is (this is typically what a VHDL/SystemVerilog compiler would do). In
the Mealy case the implementation is straightforward, but the output will be one clock
cycle ahead of the desired sequence (compare i gures 5.15b and 5.15c).
5.4.11 LCD, I
2
C, and SPI Interfaces
Three special additional design examples are presented in chapter 14, consisting of
circuits for interfacing with alphanumeric LCD displays and for implementing I
2
C or
SPI serial interfaces. Depending on the application, any of the three FSM categories
might be needed in these circuits; for instance, in the LCD driver example of section
14.1, a category 1 FSM is employed, whereas in the I
2
C and SPI serial interfaces of
sections 14.2 and 14.3, categories 2 and 3 are used.
5.5 Exercises
Exercise 5.1: Machine Category and Number of Flip-Flops
a) Why are the state machines in i gures 5.3, 5.9c, and 5.13e (among others) said to
be of category 1?
b) How many DFFs are needed to implement each of these FSMs using (
i
) sequential
encoding, (
ii
) Gray encoding, or (
iii
) one-hot encoding?
Exercise 5.2: Metastability and Synchronizer
a) Solve exercise 2.2 if not done yet.
b) Consider now the garage door controller of i gure 5.9. (
i
) Which inputs are asyn-
chronous? (
ii
) If no debouncing circuits (which are synchronous) are adopted for the
asynchronous inputs, are synchronizers indispensable in this application?
Exercise 5.3: Need for Reset
a) Solve exercise 3.10 if not done yet.
b) Solve exercise 3.11 if not done yet.
