Hardware Reference
In-Depth Information
writeB
(
ALUout
is stored in B). Observe also the presence of a
wait
time slot after every
data storage, which is needed for the data to be effectively ready for comparison before
an actual comparison occurs (recall comment 4 of section 3.13).
A corresponding state transition diagram is presented in i gure 5.13e, which is a
direct translation of the timing diagram (compare the values in the plots against those
in the state transition diagram). Note that after each write-enabling state (
load
,
writeA
,
and
writeB
) the machine goes unconditionally to the
wait
state. In the
idle
state,
wrA
=
wrB
= '0', so nothing can be written into the registers, and because
ALUop
= 0, the output
is
ALUout
= A, so the computed GCD value is kept unchanged until
dv
is asserted again.
VHDL and SystemVerilog implementations for this control unit are presented in
sections 6.8 and 7.7, respectively.
5.4.9 Generic Sequence Detector
This is another interesting example from a conceptual point of view. Say that we want
to design a signature detector that searches for the string “
abc
” in a sequential data
stream, examining one character at a time (a character here represents a bit vector
with any number of bits). So this is exactly the same problem presented in the very
i rst state transition diagram of the topic (i gure 1.3, repeated in i gure 5.14a). In this
example it was assumed that
a
c
, so this machine works well. But let us consider
now a completely generic situation, in which
a
,
b
, and
c
are
programmable
, so we can
no longer assume that they are all different. Will this machine still work?
≠
b
≠
Figure 5.14
Generic string detection. (a) Nongeneric case (requires
a
c
). (b) Completely generic imple-
mentation due to the inclusion of priorities in the transition conditions. (c) Example for the case
of
a
=
b
=
c
.
≠
b
≠
