A Fast Mode Decision Algorithm and Its Hardware Design for H.264/AVC Intra Prediction - Advances in Image and Graphics Technologies - page 55

Table 5. Synthesis Result Of Intra Prediction

FPGA Device Xilinx Virtex 5

Pixel Parallelism 16 pixels

36Kb BRAMs 10

Max.freq. (MHz) 184.8

LUTs 4699

Throughout (MB/s) 2.888 M

Table 6. Contrasts With Related Work

[5] [6] [7] This work

FPGA Device Altera Stratix II Altera Stratix II Xilinx Virtex 2 Xilinx Virtex 5

Cycles/MB 36 -- -- <160

Max.freq/MHz 98.43 153 120 184.8

LUTs 3267 -- 16546 4699

In the proposed architecture, with pipelining and parallel architecture, we can ob-
tain 16 prediction pixels concurrently. Moreover, the throughout achieved by the pro-
posed architecture is higher than the published results in [5,6,7], which make it possi-
ble to satisfy the requirement for the real time encoding.

5 Conclusion

An effective architecture is designed for intra prediction algorithm. By exploiting the
inherent spatial correlation existing in the neighbor pixels and prediction modes, a
significant computational saving can be achieved. With the hardware design, a paral-
lel and configurable architecture is adopted to speed up the encoding time and at the
same time it allows to reduce the computational complexity without any coding per-
formance loss. The maximum clock frequency of the proposed hardware architecture
can achieve 184.8 MHz in the Xilinx Virtex-5 FPGA. The experimental results con-
firm that the architecture can completely satisfy the real-time requirement for HDTV
(1920×1080) video at 60 fps.

References

1. Wiegand, T., Sullivan, G.J., Bjøntegaard, G.: Overview of the H. 264/AVC Video Coding
Standard. Circuits and Systems for Video Technology 13(7), 560-576 (2003)
2. Sahin, E., Hamzaoglu, I.: An Efficient Hardware Architecture for H.264 Intra Prediction
Algorithm. In: Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6.
Nice (2007)