Hardware Reference
In-Depth Information
4.9 High Accuracy CMOS Current Conveyors
In reference [ 44 ] Hassanein, Awad and Soliman presented a new CMOS CCII which
is characterized by high precision in voltage tracking and which also exhibits a very
low input resistance at port X. In fact they have proposed two architectures: the first
one is referred by them as high accuracy CCII while the second is referred as high
accuracy CCII with adaptive offset cancellation. Their first proposition is shown
in Fig. 4.9a . In the circuit of Fig. 4.9a the MOSFETs M 1 -M 2 ,M 3 -M 5 ,M 7 -M 9 and
M 11 -M 13 are assumed to be matched. Now assuming that all the transistors are
operating in saturation, it is seen that MOSFETs M 10 -M 13 , all of which are derived
by a constant voltage bias V B , serve as constant current sources. The dimensions of
these transistors are chosen such that the drain currents of M 12 and M 13 are each
equal to I B whereas the drain current of M 10 is fixed as 2I B . The action of the current
mirror M 3 -M 4 , coupled with the equilibrium achieved by the feedback control,
forces equal currents of value I B in the two MOSFETs of the differential pair
M 1 -M 2 . In turn, this forces gate-to-source voltages of M 1 and M 2 to be identical,
as a consequence of which, one obtains V x ¼
V y . Since M 8 and M 9 carry the same
current as M 7 and since M 12 and M 13 carry equal currents each equal to I B , it follows
that i z will be same as i x . Since I y is already equal to zero, the circuit, thus, realizes a
CCII+.
The offset cancelling mechanism of this circuit can be explained as follows. The
voltage offset of this circuit is given by the following equation:
s
I B
ʼ n C ox W 1 =
ʔ
V
¼
V x
V y λ n V D 1
½
ð
V D 2
Þ
ð
4
:
10
Þ
L 1
where
ʻ n is the channel length modulation parameter; V D1 and V D2 being the drain
voltages of MOSFETs M 1 and M 2 . It is, therefore, clear that offset can be cancelled
by making V D1 and V D2 identical. It may be noted that I D10 is taken equal to 2I B .
Now to ensure that I D4 ¼
I D5 ¼
I B , it is required that I D11 should be made (1/2)/
I D10 ¼
I B .
s
I D 4
ʼ p C ox W 4
s
I D 5
ʼ p C ox W 5
ð
V D 1
V D 2
Þ ¼
ð
4
:
11
Þ
L 4
L 5
Although this mechanism of offset cancellation is independent of input current and
input voltage, still the required doubling of current cannot be achieved precisely
because of drains of M 10 and M 11 are at different voltage levels.
To circumvent this problem, Hassanein et al. proposed [ 44 ] a modified version of
their circuit which is shown here in Fig. 4.9b .
In the circuit of Fig. 4.9 b the added mosfets M 14 is matched to the mosfets M 4
and the added M 15 is matched to M 11 . Thus the drain current of M 4 is recreated in
M 14 which through the mirror M 15 M11 is delivered to M 5 thus ensuring I d5 ¼
I d4 .
Thus, the additional circuit implements an adaptive offset cancellation technique.
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