Hardware Reference
In-Depth Information
4.2 Simple CMOS Realizations of CCII+ and CCII
Two simple CMOS realizations of CCIIs were proposed by Surakampontorn
et al. in [
5
] which are shown in Fig.
4.2a, b
. The circuit of Fig.
4.2a
implements a
CCII+. In this circuit, it can be observed that MOSFETs M
3
-M
6
and M
7
-M
8
represent, respectively, current repeater and current mirror. The basic core of the
circuit consists of transistors M
1
and M
2
and the transistors M
1
-M
2
as well M
3
-M
4
are well-matched such that (W/L)
1
/(W/L)
2
¼
(W/L)
3
/(W/L)
4
. It can be seen that the
drain currents of M
1
and M
2
are identical so that V
GS1
and V
GS2
will cancel out each
other and as a consequence, V
x
¼
V
y
will be attainable. By simple inspection of the
various currents shown on the circuit diagram, it can be observed that the source
current of M
1
and the drain current of M
7
are equal which will force I
y ¼
0. On the
other hand, with I
1
¼
I
2
, the node equation at node Z will yield I
z
¼
I
x
. Thus, the
circuit of Fig.
4.2a
implements a CCII+.
The circuit of Fig.
4.2b
is obtained from that of Fig.
4.2a
by adding an NMOS
current mirror consisting of MOSFETs M
9
-M
10
. Since the rest of the circuit com-
prised of MOSFETs M
1
-M
8
is exactly same as in the circuit of Fig.
4.2a
, it follows
that I
y
¼
0 and V
x
¼
V
y
. Furthermore, as the location of the DC bias current source I
2
has been changed, the node equation at node Z modifies to I
2
-i
z
¼
I
1
+i
x
and
therefore, with I
2
¼ I
1
, it follows that i
z
¼
i
x
and the circuit, thus, realizes a CCII
.
The authors of [
5
] have carried out a detailed non-ideal analysis of their
proposed circuits from where they have estimated the values of the non-ideal
parameters to be R
x
which are quite low and quite high
respectively as desired. Both the circuits were constructed on proto-boards where
all the devices were realized using IC CD4007 CMOS transistor arrays with DC
bias current I
1
set to 200
3.7
Ω
and R
y
9.8 M
Ω
A. The circuits were found to exhibit an excellent
linearity of the voltage transfer characteristics between V
y
and V
x
and current
transfer characteristics between I
z
and Ix with 3-dB bandwidth of the order of
several MHz in both the cases.
ʼ
4.3 Low-Voltage CMOS Current Conveyor
A MOS current conveyor design suitable for VLSI implementation was proposed
by Cheng and Toumazou in [
9
]. The basic architecture proposed by them is based
upon two generic circuits. The first of these circuits, composed of MOSFETs M
p1
,
M
n3
,M
p3
and M
n7
, is essentially a voltage follower circuit which has an in-built DC
offset cancellation scheme. On the other hand, the second generic circuit consisting
of M
n2
and M
p2
is a basic N-channel and P-channel MOSFET V
GS
matching circuit.
These basic circuits along with two PMOS mirrors shown in the diagram symbol-
ically as PMOS CM
1
and PMOS CM
2
and NMOS current repeater comprised of
MOSFETs M
n4
,M
n5
,M
n6
and M
n1
constitute the final circuit as shown in Fig.
4.3
.
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