Hardware Reference
In-Depth Information
Q
2
Q
1
I
out
(t)
I
in
(t)
output
input
Q
3
Q
4
I
a
I
b
−V
Fig. 3.13 Basic circuit of the current mirror with controllable gain proposed by Fabre and
Mimeche [
13
]
+V
I
b
Ia
Q
19
Q
15
I
0
Q
16
Q
20
Q
18
Q
17
Q
1
Q
2
Q
4
Q
3
i
y
(t)
i
x
(t)
i
z
(t)
Y
Z
X
V
y
(t)
Q
5
V
x
(t)
V
z
(t)
Q
6
Q
7
Q
14
Q
8
Q
12
Q
9
Q
13
Q
11
I
0
I
a
I
b
Q
10
−V
Fig. 3.14 Implementation of CCII+ with controllable gain [
13
]
I
out
¼
GI
0
þ
ð
It
ðÞ
Þ
ð
3
:
11
Þ
I
a
I
b
where
G
¼
ð
3
:
12
Þ
It may be seen that the architecture of CCII+ with controllable gain (Fig.
3.14
)
essentially consists of eight transistors translinear cell between inputs Y and X
which yields I
y
¼
V
y
whereas the circuit employed to sense the current i
x
and to convey the same current at Z port has been replaced by two modified circuits
0 and V
x
¼
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