Hardware Reference
In-Depth Information
+V
Q
13
Q
15
Q
14
Q
5
Q
1
Q
7
Q
2
Y
X
Z
Q
3
Q
8
Q
4
Q
6
I
0
Q
9
Q
12
Q
11
Q
10
−V
Fig. 3.11 A possible implementation of the CCII+ with reduced parasitic resistance, based upon
the proposition of Seguin and Fabre [
11
]
By a straight forward analysis of the circuit assuming a load R
L
connected at the
X port, the equivalent input impedance looking into port Y is found to be:
2
R
X
þ
R
Y
¼
2
β
ð
R
L
Þ
ð
3
:
9
Þ
which is
times larger than the Y-port input resistance of the conventional CCII,
based upon the core circuit comprised of the four transistors
mixed translinear cell
(MTC).
The validity of this technique was confirmed by bread boarded versions of the
circuit implemented from transistor arrays MPQ 2222 (for the NPN transistors) and
MPQ 2907 for the (PNP transistors) which have demonstrated that as compared to
R
y
<
β
for the conventional design, the new architecture exhibits a value of
R
y
as high as 10 M
100 K
ʩ
ʩ
for a load resistance of 1 K
ʩ
for the circuit architecture of
Fig.
3.12
.
3.2.10 Bipolar CCII with Controllable Gain
In many applications, it may be useful to have the current gain of the CC adjustable
which could be useful for electronic control of the parameters of the functional
circuits build from CCs of this type. Fabre and Mimeche [
13
] presented a new CCII
architecture in which the current transfer from port X to port Z is controllable by an
external bias current. The key idea of their proposition is a current mirror with
adjustable gain which is shown in Fig.
3.13
. If the input current I
in
(t)
¼
I
0
+ I(t) is
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