Hardware Reference
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Wilson current mirror
+V
+V
+V
I 2
I B
+V
I 2
I A
I A
I B
I 0
I 0
Q 1
Q 2
Q 4
Q 5
Q 3
Temperature
compensation circuit
R
Q 10
Q 6
Q 7
Q 8
Q 11
Q 9
−V
−V
Fig. 3.9 Bias circuit for temperature compensation [ 10 ]
from which we see that R x has now become temperature insensitive. The work-
ability of this temperature-insensitive CC has been confirmed by realizing the
circuit using PNP transistors Q2N2905 and NPN transistors Q2N3904 and it has
been found that X port input resistance nearly remains invariant at a nominal value
of 100
for a temperature variation from 10 to 90 .
ʩ
3.2.8 CCII with Reduced Parasitic Resistance R x
Seguin and Fabre [ 11 ] presented a new architecture for the CC which is shown here
in Fig. 3.11 . As can be seen, this implementation has two supplementary transistors
added as compared to the traditional implementation. Assuming the
β
of the
transistors to be identical and assuming that i x <<
2I 0 , the input current at port X
is divided into two equal parts which respectively flow in the collectors of Q 5 and
Q 7 so that the time-varying components of the currents are each equal to i x (t)/2.
This, in turn, induces time variant base currents for the transistors Q 5, Q 6, Q 7 and
Q 8 , each equal to i x (t)/2
. As a consequence, a time-variant value of the collector
currents of the transistors Q 2 and Q 4 are each approximately equal to i x (t)/
β
.
Therefore, at low frequencies, the parasitic equivalent input resistance looking
into port-X is given by:
β
V T
2 I 0
2 r x
β
r x ¼
ð
3
:
8
Þ
Through SPICE simulations, using the model parameters for the transistors from
2
ʼ
m HF2CMOS technology from SGS Thomson, with DC power supplies
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