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V DD
M p2
M p4
M p0
M p3
M p1
I 0
Q 1
Q 2
Y
X
Z
M n1
M n4
M n2
M n3
Fig. 16.3 Low-voltage CCCII proposed by Psychalinos and Souliotis (Adapted from [ 19 ] © 2010
Springer Science + Business Media)
e vX vY
I 0 þ
i x ¼
I 0 :
ð
16
1
Þ
:
v T
Expending the right hand side of the above equation into Taylor series and
considering a first order approximation the X port current is related to the differ-
ential input V x -V y according to the following formula
I 0
V T :
i x
v x
v y
ð
16
2
Þ
:
From which it is seen that R x
V T /I 0 .
This topology has following advantageous features as compared to the tradi-
tional bipolar CCCII architecture.
(i) The minimum power supply requirement is equal to V BE +2V DS,sat instead of 2
(V BE +V CE, sat ). In view of this it is seen that this architecture has a capability
for operation in a relatively lower voltage environment.
(ii) Whereas in the conventional translinear structure the translinear loop is formed
from two pairs of npn and pnp transistor, in the present case the translinear loop
is made in only single pair of npn transistor. Thus, the drawback of limited
performance of the integrated pnp transistor (such as a low value of
and high
parasitics) are eliminated and therefore this topology should be capable of
operating at relatively higher frequency. Furthermore the handling of AC
signals by PMOS transistor is avoided which is also helpful in improving
maximum frequency of operation.
β
The new CCCII offers a bandwidth of the current gain in excess of 100 MHz and
can operate from a single low voltage DC power supply of 1.5 V.
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