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PNP CM
+V CC
I B
I A
I C3
(I B − I C3 )
I C4
Q 2
Q 3
Q 4
Q 1
I XN
I Z
Y
Z
V Y
V X
X
Q 5
Q 8
I C8
Q 6
Q 7
(I B − I C7 )
I C7
I A
NPN CM
I B
−V EE
Fig. 16.2 Simplified version of the schematic of a CCCII [ 18 ]
16.3.2 Bi-CMOS CCCII Realizations
In view of the potential applications of the CCCII in making available
electronically-tunable circuit functions, several authors have tried to improve
upon the basic structure of the CCCII itself. An interesting innovation in this regard
has been to combine the best properties of the BJTs and the MOSFETs thereby
resulting in the proposal of Bi-CMOS CCCII realizations. It may be recalled that in
conventional realization of the CCCII, as well as in the Bi-CMOS CC proposed
earlier, PNP transistors are also engaged for handling the AC signals and conse-
quently, the maximum frequency of operation of the realized CCCIIs is signifi-
cantly reduced. Recently, Psychalinos and Souliotis [ 19 ] have presented a new
CCCII topology for Bi-CMOS implementation (shown in Fig. 16.3 ) which offers
the advantage of low voltage operation as well as improvement in the maximum
frequency of operation. It is shown that a slight modification in the topology also
enables to obtain negative intrinsic resistance R X .
In the low voltage CCCII topology under consideration, a two BJT translinear
loop with MOS current mirrors for DC bias current supply as well as duplication of
X-port current to yield same current at the Z port has been incorporated. This circuit
is shown in Fig. 16.3 .
According to the translinear principle the currents in transistors Q 2 and Q 1 are
related according to the following equation.
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