Hardware Reference
In-Depth Information
15.7 Wide-Band Impedance Matching Circuits
Another novel application of CCs was proposed by Godara and Fabre [
17
,
18
] who
demonstrated that a CC can be used as a versatile wide band impedance matching
device offering a vastly superior performance as compared to the other traditional
passive elements solutions. The CC based impedance matching configuration is the
first flexible matching circuit to adapt to any impedance to any desired value and is
also the smallest matching circuit ever and is a rare example of really wide band
matching. The schematic presentation of the new matching impedance circuit is
shown in Fig.
15.14
which is, in fact, a CCCII configured as voltage follower. The
basic core of the impedance conversion circuit is composed of BJTs Q
1
-Q
2
Q
3
-
Q
4.
The DC bias current I
0
is copied to the required branches of this translinear cell
through a current repeater M
1
-M
2
M
5
.
The input V
in
is applied at port-Y which has a very high intrinsic resistance R
y
. The
output is taken from port-X where the output impedance consists of resistance
R
x
¼
M
3
and current mirror composed of M
4
V
T
/2I
0
(where V
T
is the thermal voltage) in series with a small parasitic
inductance L
x
. It is important to note that different value of R
x
can be obtained
by changing the DC bias current I
0
.
15.8 Sample and Hold Circuits
A simple CC-based sample and hold circuit presented by Hwang et al. [
19
] is shown
in Fig.
15.15
. The circuit is operated from the clock signal
˕
1
is HIGH,
the circuit is in sample mode and the input signal V
in
is sampled and stored across
the capacitor C
1
. When
˕
1
. When
˕
1
is LOW the circuit is in hold mode and the output V
out
will be copied from the voltage sampled across C
1
. The output voltage is, therefore,
given by
V
out
¼
α
v
V
in
where
α
v
is the voltage gain of the current conveyor between
ports X and Y; the other characterizing equations being
i
y
¼
0 and
i
z
¼
α
i
i
x
where
both
α
i
are nominally unity.
Another sample and hold circuit proposed by Hwang et al. [
20
] is shown in
Fig.
15.16
which employs a fully balanced CCII (FBCCII). When clock
α
v
and
˕
1
is HIGH
the circuit is in sample mode and the input signal is sampled on the capacitor C
s
.
When
˕
1
is LOW the circuit is in hold mode and input signal is held by the capacitor
C
s
simultaneously. The outputs of the sample and hold circuit namely V
XP
and V
XN
trace the input signals V
YP
and V
YN
and can be expressed as:
1
V
out
¼
V
XP
V
XN
¼
ð
V
YP
V
YN
Þ
ð
15
:
63
Þ
1
Aʲ
1
þ
where
A
is the DC gain of the FDCCII and
ʲ
is the feedback factor of FDCCII which
is equal to unity.
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