Hardware Reference
In-Depth Information
Fig. 15.3 CCII-based
LNAs [
3
](a) symbolic
representation (b) transistor
level implementation
a
V
0
I
B1
I
B2
V
in
y
y
CCCII+
x
CCCII+
z
1
2
z
x
b
V+
I
02
I
01
(I
01
+I
x1
)
Q
1
Q
2
Q
3
I
x1
(I
02
+I
x1
)
+
I
02
+
−
I
01
V
in
V
0
−V
−
frequency responses from zero to 3GHz and (iii) easy control of the gain by the ratio
of two DC bias currents over a wide range (0 dB to 20 dB).
A straight forward analysis of the circuit of Fig.
15.3
shows that its voltage gain
is given by
V
o
V
in
¼
r
x
2
r
x
1
ð
15
:
16
Þ
V
T
1, 2, it follows that,
V
o
I
B
1
Since
r
xi
¼
2
I
Bi
,
i
¼
V
in
¼
I
B
2
where I
B1
and I
B2
are respectively
the DC bias currents of CCCII1 and CCCII2.
Likewise, a detailed analysis of the transistorized version (Fig.
15.3b
) also
demonstrates that its voltage gain is given by the ratio of the control current I
02
and the bias current I
01
i.e.
V
o
V
in
¼
I
01
I
02
ð
15
:
17
Þ
It has been suggested that since the noise of this LNA is demonstrated by the base
resistance of transistor Q
1
and the collector current I
c
, the emitter length was
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