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Fig. 14.8 CMOS
realization of the MICCII-
[ 19 ]
+V DD
V c
M 8
M 2
M 5
M 3
x
z
M 6
M 4
V b
M 7
y
M 1
V SS
The circuit was tested using the CMOS MICCII of Fig. 14.8 with
2.5 bias
voltage, with V B ¼
m CMOS model
parameters were chosen. The simulated inductor was used to design a third order
Butterworth high pass filter designed for a cut off frequency of 1.59 MHz. Close
correspondence between simulation generated frequency response and the theoret-
ical one confirmed the viability of the proposed circuit.
0.604 and V c ¼
0.25 V. TSMC 0.35
μ
14.8 DO-CCII-Based Synthetic Floating Immittances
Minaei et al. [ 21 ] presented a structure as shown in Fig. 14.9 which uses two
DO-CCIIs and three passive components to realize general floating impedance. The
configuration can simulate an FI, floating capacitance (FC), floating FDNR and
floating admittance converter (FAC) without any passive component matching
condition, subject to the appropriate choice of various circuit admittances. Assum-
ing ideal DO-CCIIs, an analysis of this circuit yields the following short circuit
admittance matrix:
y 1 y 2
y 3
1
1
½ ¼
Y
ð
14
:
14
Þ
11
Now depending upon the selection of the various passive components, the follow-
ing floating elements can be obtained: If one selects y 1 and y 2 as resistors with y 3 as
capacitor, an FI is realized; if y 1 and y 3 are chosen as resistors with y 2 as a capacitor,
an FC is realized; if y 1 and y 2 are taken as capacitors with y 3 as a resistor, an FDNR
is simulated and finally, if y 1 and y 3 are chosen as resistors, with y 2 ¼
y(s) the circuit
functions as a FAC. In the realizations of FC, FDNR and FAC only resistors are
 
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