Second Generation Applications of Other Types of Current Conveyors in Realizing Synthetic Impedances - Current Conveyors: Variants, Applications and Hardware Implementations - page 463

Fig. 14.5 The
configuration proposed by
Yuce for the realization of
positive/negative parallel
R-L impedances (Adapted
from [ 17 ] © 2006 Springer)

y 1

I in

DVCC±

z

V in

y 2

x

Y in

R 2

C

R 1

demonstrated by Zeki and Toker in [ 16 ] by realizing a gyrator and a simulated
inductor with the feature of electronic-controllability through external gate control
voltages applied to the MOSFETs.
The gyrator circuit proposed by Zeki and Toker in [ 16 ] is shown here in
Fig. 14.6a . By a straight forward analysis, the y-matrix of this circuit is found to be:

C ox L 2 V G 2 0 2 μ ð V th Þ

C ox L 1 V G 1

½ ¼ Y ð 14 : 7 Þ

μ ð V th Þ

2 0

In view of the above, it is obvious that this gyrator can be used as a simulated
inductor by terminating either port 2 or port 1 into a grounded capacitor. For
instance, with a capacitor C 1 connected at port 2, the input impedance looking
into the port 1 is given by:

sC 1

2 C ox L 1 L 2 V G 1

Z in ¼ ð 14 : 8 Þ

4 μ ð V th Þ ð V G 2 V th Þ

Hence, grounded inductor value (L eq ) is given by:

C 1

2 C ox L 1 L 2 V G 1

L eq ¼ ð 14 : 9 Þ

4 μ ð V th Þ ð V G 2 V th Þ

which can be controlled by V G1 or V G2 or by both.
The validity of the DXCCII-based gyrator of Fig. 14.6a was verified by realizing
a CM biquad filter (see Fig. 14.2b of [ 16 ]) wherein the CMOS DXCCII from [ 56 ]
was used to simulate the inductor with 2.5 V DC power supplies and biasing

current of I B ¼100 μ A using BSIM3v3 model parameters of AMS 0.35 μ m CMOS
process. The capacitors of values C 1 ¼ 10 pF were used. The channel

length (L) and channel width (W) for MOSFETs M 1 and M 2 was taken as 1.5

7 pF and C 2 ¼

m.
The variation of cutoff frequency with gate voltage is shown in Fig. 14.6b which
confirms the validity of the simulated inductor.

μ