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a
b
x
CCIII+
x
z+
Y
ina
CCIII+
y
z+
R
1
y
C
0
C
0
R
1
Y
inb
R
2
R
2
c
d
y
y
CCIII−
CCIII−
z
−
Y
inc
z−
x
R
1
Y
ind
x
R
1
C
0
C
0
R
2
R
2
Fig. 14.3 Some Minimal realizations of R-L immittances using a single CCIII as proposed by
Wang and Lee [
10
]
14.5 Grounded R-L and C-D Immittances
Using a Single DVCC
Circuits for the simulation of grounded series R-L and parallel R-L immittances
employing a single DVCC, a grounded capacitor and two resistors, without any
component- matching-constraints, were proposed by Incekaraoglu and Cam in [
14
]
and are shown here in Fig.
14.4
. Series C-D and parallel C-D immittances can be
obtained from the same circuits by applying RC: CR transformation. A routine
circuit analysis, assuming ideal DVCC, yields the following expressions:
V
in
I
in
¼
Z
ina
¼
ð
R
1
þ
R
2
Þ þ
sC
0
R
1
R
2
ð
14
:
4
Þ
and
I
in
V
in
¼
1
R
1
þ
1
R
2
1
sC
0
R
1
R
2
Y
inb
¼
þ
ð
14
:
5
Þ
Hence, the circuit of Fig.
14.4a
simulates series R-L impedance while the circuit of
Fig.
14.4b
simulates a parallel R-L admittance.
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