Second Generation Applications of Other Types of Current Conveyors in Realizing Synthetic Impedances - Current Conveyors: Variants, Applications and Hardware Implementations - page 460

Fig. 14.2 Floating FDNR
employing two DVCCs
proposed by Sedef and
Acar [ 8 ]

z 2

y 2

I 1

V 1 y 1

DVCC

z 1

x

Z 1 Z 3

y 2

z 2

y 1

DVCC
z 1

V 2

x

I 2

Z 2

components by formulating a generalized four-node structure (including one node as
a ground) in which a CCIII was embedded with its three terminals terminated into
the remaining three nodes of the structure. This generalized configuration gave birth
to a number of special cases out of which here we have included four specific circuits
which have the desirable feature of employing a grounded capacitor and the use of a
minimum of only two resistors. These circuits are shown in Fig. 14.3 . The circuits of
Fig. 14.3a and b use non-inverting CCIII while the circuits of Fig. 14.3c and d
employ inverting CCIII. Assuming ideal CCIII

, an analysis of these circuits gives:

1
R 1 þ

1
R 2 þ

1
sC 0 R 1 R 2 ¼

Y ina ¼ Y inc ð 14 : 2 Þ

and

Z inb ¼ R 1 þ R 2 þ sC 0 R 1 R 2 ¼ Z ind ð 14 : 3 Þ

From the above expressions, it is clear that the circuits of Fig. 14.3a and c simulate a
parallel R-L immittance while Fig. 14.3b and d simulate a series R-L immittance
without the requirements of any component-matching or cancellation condition.
Furthermore, the application of the RC: CR transformation on these four circuits
would yield circuits capable of simulating parallel C-D and series C-D immittances
respectively.
For verifying the workability of the circuits, a CMOS CCIII proposed by
Piovaccari [ 55 ] with level 28 MOS model parameters provided by TSMC 0.6

μ m

CMOS technology were employed. The biasing supply was 2.5 V and the circuits

were used to realize simple filters whose SPICE simulation results were found to be
in good agreement with theory.