Hardware Reference
In-Depth Information
Fig. 14.1 Floating
inductance simulation using
DOCCII proposed by
Ananda Mohan [
7
]
z
x
1
−
R
1
DOCCII
y
z
−
C
0
z
y
2
+
DOCCII
x
z
−
R
2
grounded. Their proposition is shown here in Fig.
14.2
and is characterized by the
Y-matrix:
1
Z
3
Z
1
Z
2
1
½
¼
Y
ð
14
:
1
Þ
11
It may be noted that from the same circuit, it is possible to realize a lossless floating
inductance by choosing Z
1
and Z
2
as resistors and Z
3
as a capacitor and an ideal
FDNR by choosing Z
3
as a resistor and Z
1
and Z
2
as capacitors. In both the cases, it
is possible to realize variable elements through a single variable resistance. Fur-
thermore, with the resistor implemented by MOSFET-based voltage-controlled
grounded resistor such as the one in [
54
], the circuit can also realize
electronically-variable floating inductance or floating FDNR.
The workability of this circuit has been verified by using a CMOS DVCC (see
Fig.
1b
of [
8
]) based on 1.2
m CMOS model parameters obtained through MOSIS.
The FDNR was used to design a 4th order Butterworth LC band pass filter with
f
0
¼
μ
20 KHz. Very good correspondence between theoretical
and simulation results was obtained which is indicative of the practical viability of
the circuit of Fig.
14.2
.
100 KHz and BW
¼
14.4 Simulated Inductors Employing CCIII
Several authors have employed third generation current conveyors (CCIIIs) to
realize a variety of simulated immittances for example see [
6
,
9
,
22
,
28
]. CMOS
realisations of CCIII are already known in literature, for example see [
11
,
55
].
Wang and Lee [
10
] presented a systematic approach to synthesize R-L and C-D
immittances employing a single CCIII along with a minimum number of passive
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