Hardware Reference
In-Depth Information
Fig. 13.11 (continued)
Assuming ideal DVCCCTA and performing routine circuit analysis of the circuit
shown in Fig.
13.11
gives the following CE:
s
2
C
1
C
2
R
x
þ
sC
1
R
x
g
m
1
ð
1
Þ þ
g
m
2
¼
0
ð
13
:
33
Þ
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