Hardware Reference
In-Depth Information
s
2
R
a
C
b
C
c
2
þ
I
0
I
in
¼
1
þ
s
3
R
a
C
b
C
c
1
C
c
2
c
2
s
2
R
a
C
b
C
c
1
þ
þ
C
c
2
C
c
3
þ
C
c
3
C
c
1
c
1
ð
2
C
c
2
þ
C
c
3
Þ
þ
sR
a
C
c
1
þ
ð
C
b
þ
C
c
3
Þ þ
2
ð
12
:
137
Þ
μ
The circuit of Fig.
12.38
was simulated [
109
] in SPICE using TSMC 0.35
m
CMOS process parameters and the circuit designed for 1 dB ripple and 50 MHz
bandwidth which is shown here in Fig.
12.38c
.
12.2.7 Filter Design Using DXCCII
The dual-X CCIIs (DXCCII) has two X-inputs on which the terminal voltages are
V
y
and
V
y
respectively. In addition it has two Z-outputs whose output currents
follow the respective X-terminal input currents, this property is particularly useful
from two different viewpoints: (i) availability of complementary signals on the two
X-input terminals helps in eliminating the square non-linearity of a MOSFET with
its drain and source terminals connected between the two X-terminals and thereby
making a linear voltage-controlled resistance realizable without requiring any
additional hardware (ii) the availability of two current outputs is itself useful for
a CM circuit design while this degree of freedom is further extended by having
multiple number of Z-outputs which only require additional current mirrors in the
internal architecture of a CMOS DXCCII. In view of the above advantages there-
fore, it is not surprising that DXCCIIs have found to be quite attractive for realizing
MOSFET-C continuous time filter in CM. A circuit highlighting these features is
given in this section.
The DXCCII can be defined by the following matrix equation:
2
3
2
3
2
3
I
Y
I
Zp
I
Zn
V
Xp
V
Xn
00000
10000
01000
00100
00
I
Xp
I
Xn
V
Y
V
Zp
V
Zn
4
5
4
5
4
5
¼
ð
12
:
138
Þ
100
Minaei biquad Figure
12.39
shows an electronically-tunable CM universal
biquad filter devised by Minaei in [
111
] using three DXCCIIs, two grounded
capacitors and four NMOS transistors. The filter structure realizes simultaneously
LPF, BPF and HPF from high output impedance nodes. With appropriate connec-
tions of output currents a notch and APF can also be obtained. The filter parameters
ˉ
0
and bandwidth can be controlled electronically.
Assuming ideal DXCCIIs and let all MOSFETs M
i
(i
4) are operating in
triode region, then the resistance of the NMOS transistors in Fig.
12.39
can be
¼
1
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