Hardware Reference
In-Depth Information
Fig. 12.19 VM universal
biquad proposed by Chen
(Adapted from [
40
]
©
2007
Springer Science + Business
Media)
V
01
DDCC
y
3
y
2
1
z+
y
1
x
C
1
V
05
R
1
V
03
R
3
V
in
DDCC
V
02
y
3
2
y
2
z+
y
1
x
C
2
V
04
R
2
can be made floating and inserting V
in
into the floating terminals of the capacitor C
1
and output is being taken at V
03
. The
ˉ
0
and Q
0
for all the cases can be given by:
r
1
C
1
C
2
R
1
R
2
r
C
2
R
2
R
1
C
1
1
R
3
ω
0
¼
and Q
0
¼
ð
12
:
76
Þ
Thus,
ˉ
0
and Q
0
can be controlled orthogonally.
Chiu-Horng biquad In 2007, Chiu and Horng [
41
] proposed a high input and low
output impedance VM MISO-type universal biquadratic filter structure using three
DDCCs, two grounded capacitors and two grounded resistors which is shown here
in Fig.
12.20
.
The circuit of Fig.
12.20
can realize all the five second-order standard fitter
responses without any component matching condition. Assuming ideal DDCCs, the
output voltage in terms of input voltages can be expressed as:
C
2
R
2
V
in
2
V
in
1
C
1
C
2
R
1
R
2
s
2
V
in
3
s
þ
C
2
R
2
V
out
¼
ð
12
:
77
Þ
s
2
þ
s
1
þ
1
C
1
C
2
R
1
R
2
The various filter responses can now be realized from the above equation as
follows:
HPF: if V
in1
¼
V
in2
¼
0 (grounded) and V
in3
¼
V
in
; BPF: if V
in1
¼
V
in3
¼
0
(grounded) and V
in2
¼
V
in
; LPF: if V
in3
¼
V
in2
¼
0 (grounded) and V
in1
¼
V
in
;
Notch:
if
V
in2
¼
0
(grounded)
and
V
in3
¼
V
in
¼
V
in1
and
APF:
if
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