Hardware Reference
In-Depth Information
Assuming ideal DO-DVCCs, a routine circuit analysis yields:
I 01 ¼
ð
sC 2 R 2 þ
1
Þ
I in 1 þ
sC 1 R 2 I in 2
1
ð
12
:
21
Þ
s 2 C 1 C 2 R 1 R 2 þ
sC 2 R 2 þ
ð
sC 2 R 1
Þ
I in 1 þ
I in 2
I 02 ¼
ð
:
Þ
1
12
22
s 2 C 1 C 2 R 1 R 2 þ
sC 2 R 2 þ
From the above equations, the following CM filter functions can be obtained:
If I in1 ¼
0, I in2 ¼
I in ;
I in LPF ¼
I 02
1
s 2 C 1 C 2 R 1 R 2 þ
If I m1 ¼
0, I m2 ¼
Im
ð
12
:
23
Þ
;
sC 2 R 2 þ
1
I in BPF
I 02
For I in2 ¼ 0, I in1 ¼ I in , and R 1 ¼ R 2 ;
sC 2 R 1
s 2 C 1 C 2 R 1 R 2 þ
¼
ð
12
:
24
Þ
sC 2 R 2 þ
1
I in HPF
I 03
If I 03 ¼
ð
I in þ
I 01
Þ
,I in1 ¼
I in , and I in2 ¼
0
;
s 2 C 1 C 2 R 1 R 2
s 2 C 1 C 2 R 1 R 2 þ
¼
ð
12
:
25
Þ
sC 2 R 2 þ
1
If I 04 ¼
(I in +I 02 ), I in1 ¼
I in ,I in2 ¼
0 and R 1 ¼
R 2 ;
I in Notch ¼
s 2 C 1 C 2 R 1 R 2 þ
I 04
1
ð
12
:
26
Þ
s 2 C 1 C 2 R 1 R 2 þ
sC 2 R 2 þ
1
and if I 05 ¼
(I 04 +I 02 ), I in1 ¼
I in ,I in2 ¼
0 and R 1 ¼
R 2 ;
I in APF ¼
I 05
s 2 C 1 C 2 R 1 R 2
sC 2 R 2 þ
1
ð
12
:
27
Þ
s 2 C 1 C 2 R 1 R 2 þ
sC 2 R 2 þ
1
For R 1 ¼
R 2 ¼
R, the filter parameters
ˉ 0 and Q 0 are given by:
r
1
C 1 C 2
r
C 2
C 1
1
R
ω 0 ¼
and Q 0 ¼
ð
12
:
28
Þ
Hence, parameters
ˉ 0 and Q 0 are orthogonally controllable.
The validity of the proposed configuration has been confirmed through PSPICE
simulations using model parameters from 0.5
μ
m CMOS technology obtained
through MOSIS.
Horng generalized first order filter The circuit shown in Fig. 12.7 is a DVCCs-
based high input impedance VM first-order LPF, HPF and APF configuration using
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