Hardware Reference
In-Depth Information
Using ideal DVCC, a routine circuit analysis gives the following output voltage
in terms of the various input voltages:
n
o
V
1
þ
V
3
s
2
s
R
2
1
1
C
1
s
s
1
C
1
C
2
R
1
R
2
þ
C
2
C
1
R
2
V
2
þ
C
1
R
1
þ
V
0
¼
ð
12
:
5
Þ
Ds
ðÞ
1
R
1
C
1
þ
1
R
2
C
2
1
C
1
C
2
R
1
R
2
s
2
where
D s
ðÞ¼
þ
s
þ
ð
12
:
6
Þ
From equations (
12.5
) and (
12.6
), the following filter responses can be obtained:
LPF: if V
1
¼
0 (grounded),
V
2
¼
V
3
¼
V
in
(input voltage) and R
1
¼
R
2
; BPF:
V
1
¼
V
in
,
R
1
¼
R
2
and C
1
¼
C
2
; Notch: V
1
¼
V
2
¼
V
3
¼
V
in
,R
1
¼
R
2
and C
1
¼
C
2
and
APF: V
1
¼
0
¼
V
3
,V
2
¼
V
in
and (R
2
/R
1
+C
1
/C
2
)
¼
1; HPF: V
2
¼
0
¼
V
3
,V
1
¼
1
An examination of the above filter realizations reveals that the circuit suffers
from the realization conditions/constraints as well as non-availability of high input
impedance, although it has the advantage of employing only one active element.
V
2
¼
V
3
¼
V
in
and (R
2
/R
1
+C
1
/C
2
)
¼
Horng-Jhao biquad Horng and Jhao [
5
] have presented a VM MIMO-type
universal biquad using a DVCC, two resistors and two capacitors as shown in
Fig.
12.4
.
The circuit can realize all the standard second-order filter responses without
altering the circuit topology. Assuming ideal DVCC, the three voltage outputs can
be obtained in terms of four inputs as follows:
V
in
3
þ
V
in
2
þ
V
in
1
C
1
C
2
s
2
1
Ds
1
R
1
1
R
2
1
R
2
1
R
1
R
2
V
01
¼
þ
sC
2
sC
1
ðÞ
1
R
2
V
in
4
1
R
1
sC
1
þ
ð
12
:
7
Þ
z+
y
1
+
1
C
1
V
02
DVCC
y
2
z+
+
x
2
+
V
in2
R
1
C
2
V
01
-
+
+
+
+
R
2
V
in1
V
03
V
in3
V
in4
-
-
-
Fig. 12.4 VM biquad using
single DVCC [
5
]
-
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